The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for capacitor plates is conductively doped polysilicon. Such is utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying topography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors and the reactor used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such prior art techniques are inherently unpredictable or inconsistent in the production of a rugged polysilicon film.
One type of polysilicon film which maximizes a roughened outer surface area is hemispherical grain (HSG) polysilicon, which is typically provided to a thickness of from 300 Angstroms to 400 Angstroms. Such can be deposited or grown by a number of techniques. One technique includes direct LPCVD formation at 590.degree. C. Another includes formation by first depositing an amorphous silicon film at 550.degree. C. using diluted SiH.sub.4 (20%) gas at 1.0 Torr, followed by a subsequent high temperature transformation anneal. HSG polysilicon is typically not, however, in situ doped during its deposition due to undesired reduction in grain size in the resultant film or inherent failure of HSG to form. Accordingly, other methods are utilized to conductively dope the HSG polysilicon after its deposition. To provide such doping, an underlayer of heavily doped polysilicon can be provided, with subsequent doping of the HSG polysilicon layer occurring by an annealing step to drive the dopant into the HSG layer. Alternately, dopant can be implanted into the polysilicon after its deposition from above, although such may adversely affect grain shape having a tendency to smoothen the deposited HSG layer.
One example prior art method for providing doped HSG poly is as follows. A first doped layer of polysilicon is typically deposited to serve as a substrate for the HSG polysilicon. Then, a thin undoped amorphous layer of silicon is deposited. This layer is then subjected to an inert low pressure atmosphere, followed by a higher pressure atmosphere in the presence of a flowing purge gas, followed by exposure to another inert low pressure evacuation atmosphere. Subsequently, an annealing step is conducted in an inert atmosphere to transform the undoped amorphous silicon layer into undoped HSG polysilicon. Subsequent doping of the HSG layer can be accomplished by out-diffusion from the underlying polysilicon layer if it has previously been highly conductively doped. Alternately, ion implantation can be used to conductively dope the formed HSG layer.
The prior art has attempted to provide such HSG layers as being in situ conductively doped, but without much success. For example, the amorphous silicon layer from which the HSG polysilicon is produced has been deposited to be conductively doped. However, such dopants somehow adversely affect HSG grain growth as HSG polysilicon does not result from a subsequently conducted annealing step.
Accordingly, needs remain for producing HSG layers which are in situ conductively doped during formation.